The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei 11-334971 filed in Nov. 25, 1999 and the Japanese Patent Application No. Hei 2000-287191 filed in Sep. 21, 2000 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
1. Field of the Invention
The present invention is related to a semiconductor memory device such as a static random access memory, and more particularly related to a semiconductor memory device implemented with a test circuit.
2. Prior Art
In the recent years, the increase in the storage capacity and the improvement of the power saving structure on the standby mode of semiconductor memory devices such as the static random access memory have been advanced. The occurrence frequency of defective bit locations tends to increase as the storage capacity increases so that, in the test process, defective memory cells are replaced by redundancy memory cells in accordance with the redundancy circuitry technique in order to recover the semiconductor memory device.
It is sometimes the case, however, that there is a memory call(s) through which a leakage current exceeding the allowable value is passed while the static random access memory including the defective memory cell normally operates without a problematic function. If there is such a memory cell, the consumption current in the standby mode is increased which decreases the device yield.
In accordance with the conventional semiconductor memory device as illustrated in FIG. 1, the location of a defective memory cell is detected as a path of a leakage current by a test circuit provided within the semiconductor memory device in order to cut off the leakage path via the defective memory by selectively melting and disconnecting a laser fuse through which the defective memory is connected to the power terminal so that the defective memory is replaced by a redundancy cells.
More specifically explaining, in the case of the semiconductor memory device as illustrated in FIG. 1, a xe2x80x9cHxe2x80x9d level operation mode switching signal S6 is externally inputted to an external input circuit 92 through an external input terminal 91. By this configuration, the output signal S4 and the output signal S5 of the external input circuit 92 become at the xe2x80x9cLxe2x80x9d level and at the xe2x80x9cHxe2x80x9d level respectively. An n-type transistor Q2 receives at the gate thereof the output signal S5 being pulled up to the xe2x80x9cHxe2x80x9d level and is then turned on, and therefore the output signal S3 of a row address decoder 9 is transferred to one terminal of an NOR gate circuit 93 as the output signal S2.
By this configuration, the output signal S3 of the row address decoder 96 is pulled up to the xe2x80x9cHxe2x80x9d level while, although not shown in the figure, the remaining output signals of the row address decoder 96 to the remaining lines (not shown in the figure) is pulled down to the xe2x80x9cLxe2x80x9d level. The output signal S4 at the xe2x80x9cLxe2x80x9d level of the external input circuit 92 is input to the other input terminal of the NOR gate circuit 93 so that the output signal S1 at the xe2x80x9cHxe2x80x9d level is input to the gate of the n-type transistor Q1, which is then turned off. By this configuration, the common electric power source line g1 is separated from the electric power source, and therefore the memory cells M11 to M1n are no longer supplied with electric energy while the remaining common electric power source lines (not shown in the figure) are maintained connected to the electric power source to supply the electric power to the remaining memory cells.
Furthermore, the output signal S4 at the xe2x80x9cLxe2x80x9d level is input to the gate of the n-type transistor Q5 while the output signal S5 at the xe2x80x9cHxe2x80x9d level is input to the gate of the n-type transistor Q4 and the gate of the p-type MOS transistor. As a result, the n-type transistor Q5 and the p-type MOS transistor are turned off while the n-type transistor Q4 is turned on so that the word line w1 is grounded in order to be separated from the output signal S3 of the row address decoder. By this configuration, no current is passed through the memory cells M11 to M1m while the remaining memory cells are supplied with electric current.
It is determined, by selecting the respective lines in sequence and measuring the leakage current value for each selection in this manner, that a defective memory cell is included in the line being selected when the leakage current value is no lower than the allowable value. The defective line is then replaced with a redundancy line prepared in advance by melting the fuse F1 connected to that line to disconnect the common electric power source line g1 from the electric power source for cutting off the leakage current path.
The location of the memory cell as a leakage current path can be easily detected in this manner.
However, since recent semiconductor memory devices have been designed with large storage capacities, it is known that the memory cells of the memory cell arrays 50 are grouped into a plurality of blocks (l) to (n) in which the memory cells are arranged in matrices as illustrated in FIG. 2.
A plurality of row address decoders 52 are located for each two cells while a row selection line 53 is extended from each row address decoder 52. The row address decoder 52 serves to activate one of the row selection lines 53 as selected in accordance with the row addressing signal AIN which is input through an address decoder 60. There are provided, at a plurality of ends of the blocks, block selection circuits 70 from which are extended block selection lines 55, and word line selection circuits 56 receiving input signals from the row selection lines 53 and the block selection lines 55.
Also, each pair of the memory cells 51 are located symmetrically in the vertical direction and commonly supplied with the electric power source through a common electric power source line VL which is located in parallel with the row selection line 53.
In a normal operation mode, the memory cells 51 can be selected by selecting one of a plurality of the row selection lines 53 and one of a plurality of the block selection lines 55 in accordance with a desired address AIN and a desired address signal BIN in order to activate a desired one of the word lines 54 connected to the row selection line 53 and the block selection line 55 as selected. Data as selected can be read from the memory cells 51 by means of a read/write circuit 80 and output through an I/O terminal while desired data can be written to the memory cell 51 by means of a read/write circuit 80 through the I/O terminal.
When the semiconductor memory device is on the standby mode, all the word lines 54 are inactivated under the control of an internal circuit in response to an external signal as input.
Furthermore, in the case of recent semiconductor memory devices having been designed with large storage capacities, there are problems relating not only to the memory cell but also to the leakage current passing through a bit line, resulting in decrease of the device yield. Taking this point into consideration, when a defective function originating from a leakage current path through a bit line is recovered by the redundancy circuitry technique, the fuse elements as inserted to the electric power source connected to the bit line is disconnected by melting in order to replace the defective bit line by a redundancy cell as illustrated in FIG. 3 showing an exemplary conventional semiconductor memory device of this kind.
The conventional semiconductor memory device as illustrated in FIG. 3 is composed of a memory cell array consisting of a number of memory cells 100 arranged in the form of a matrix, control terminals (CE,WE,OE), internal circuits provided for the control terminals (a CE buffer, a WE buffer, an OE buffer), address terminals (an AINR terminal, an AINC terminal), internal circuit provided for the address terminals (row address decoders 120, a row address buffer 121, column switches 131, column address decoders 132, a column address buffer 133), I/O terminals for writing and reading data and internal circuit provided for the I/O terminals (a plurality of bit line load and pull-up and equalizer circuits 110, a data line pull-up and equalizer circuit 134, a sense amplifier and write buffer circuit 135.
Each bit line load and pull-up and equalizer circuit 110 is connected between each pair of the bit lines. A respective fuse 115 is connected between each bit line load and pull-up and equalizer circuit 110 and the power terminal VDD. The bit line load and pull-up and equalizer circuit 110 is composed of bit line load circuits 111 and 112 and bit line pull-up elements U1 and U2 and a bit line equalizer element E1. The bit line load and pull-up and equalizer circuit 110 is then activated or inactivated in accordance with the output signal xcfx861 of a bit line equalizer pull-up generation circuit 151. The data line pull-up and equalizer circuit 134 is composed of data line pull-up elements U3 and U4 and a bit line equalizer element E2. The data line pull-up and equalizer circuit 134 is then activated or inactivated in accordance with the output signal xcfx862 of the data line equalizer pull-up generation circuit 152.
The normal operation mode and the standby mode of the semiconductor memory device are implemented as follows.
In the normal operation mode, a predetermined word line and a predetermined column switch are selected in accordance with an address as given and therefore the memory cell as selected is activated to perform the read/write operation.
In the standby mode, a chip enable signal is externally input to a CE terminal in order to inactivate 811 the word lines W1 to Wm by the control operation of the internal circuit thereof. Also, all the column switches 131 become non-conductive by means of said chip enable signal. Furthermore, all thee bit line pairs B1, B1B . . . , Bn, BnB and the data lines D1 and D1B are fixed to the power potential VDD while the output signal xcfx861 of the bit line equalizer pull-up generation circuit 151 and the output signal xcfx862 of the data line equalizer pull-up generation circuit 152 are pulled to the xe2x80x9cLxe2x80x9d level.
However, there are following shortcomings in the case of the semiconductor memory device in accordance with the conventional technique as described above.
(1) In the semiconductor memory devices with large storage capacities as illustrated in FIG. 2, the location of a defective memory cell is detected as a path of a leakage current by the test process. There is a problem however not only that, while the time required for completing the test tends to be very long, but also that the test circuit as illustrated in FIG. 1 tends to occupy a substantial area resulting in the increased chip size.
(2) In the semiconductor memory devices as illustrated in FIG. 3, while the memory cells 100 serve to maintain data, the bit line pairs B1, B1B, . . . , Bn, BnB are fixed to the power potential VDD while the word lines W1 to Wm are fixed to the ground level by the control operation of the internal circuit thereof. In this case, however, there are sometimes formed a leakage current path P1 or P2. If the leakage current passed through the leakage current path P1 or P2 is sufficiently small, the redundancy circuitry technique is not applied to, while the normal read/write operation is not affected by the leakage current, and therefore the device yield is reduced when the consumption current on the standby mode exceeds the allowable value.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved semiconductor memory device comprising:
a plurality of word lines each of which is connected to a predetermined number of memory cells in the row direction;
a plurality of common electric power source lines each of which is provided for each predetermined number of rows in order to make connection with the current paths of the memory cells on said each predetermined number of rows in a row direction;
a plurality of row selection lines connected respectively to said respective word lines for the purpose of selecting a row;
row address decoders for selecting said row selection lines; and
a selection circuit connected between said common electric power source lines and an electric power source respectively for selecting one of said common electric power source lines by means of said row address decoders in order to connect the common electric power source line as selected with the electric power source and disconnect the remaining common electric power source lines from the electric power source in the case that switching to a test mode is indicated by an operation mode switching signal which is used to switch between a normal operation mode and a test mode, and for connecting all of said common electric power source lines with the electric power source in the case that said the operation mode switching signal indicate switching to the normal operation mode.
In a preferred embodiment, further improvement resides in that a fuse is provided between the electric power source and a respective one of said common electric power source lines.
In accordance with a further aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved semiconductor memory device comprising:
a plurality of word lines connected to a predetermined number of memory cells in a row direction;
a plurality of common electric power source lines each of which is provided for each predetermined number of rows in order to make connection with the current paths of the memory cells on said each predetermined number of rows in the row direction;
a plurality of row selection lines connected respectively to said respective word lines for the purpose of selecting a row;
row address decoders for selecting said row selection lines; and
a test circuit for connecting an electric power source, by selecting one of said plurality of the row selection lines, with said common electric power source line arranged corresponding to the row selection line as selected and for disconnecting the remaining common electric power source lines from the electric power source.
In a preferred embodiment, further improvement resides in that a fuse is provided between the electric power source and a respective one of said common electric power source lines.
In accordance with a further aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved semiconductor memory device comprising:
a memory cell array in which memory cells are arranged in the form of a matrix which is divided into a plurality of blocks;
a plurality of word lines provided within said memory cell array, each of said word lines being connected to a same number of memory cells in a row direction;
a word line selection circuit having input terminals connected to a row selection line for selecting a row and a block selection line for selecting a block for selecting a predetermined word line among from the plurality of said word lines;
a plurality of common electric power source lines each of which is provided for each predetermined number of rows in order to make connection with the current paths of the memory cells on said each predetermined number of rows in the row direction;
row address decoders for outputting a selection signal on the basis of a row addressing signal required for selecting said row selection lines;
a selection circuit connected between said common electric power source lines and an electric power source respectively and receiving an operation mode switching signal which is used to switch between a normal operation mode and a test mode and said selection signal as given from said row address decoders for selecting one of said common electric power source lines by said selection signal in order to connect the common electric power source line as selected with the electric power source and disconnect the remaining common electric power source lines from the electric power source in the case that switching to the test mode is indicated by said operation mode switching signal, and for connecting all of said common electric power source lines with the electric power source in the case that said the operation mode switching signal indicate switching to the normal operation mode; and
an address signal output control circuit for controlling the supply of a row addressing signal to said row address decoders on the basis of an address output control signal as externally given for the purpose of determining a defective cell in the case that switching to the rest mode is indicated by said operation mode switching signal.
In a preferred embodiment, further improvement resides in that the determination of a defective cell is performed by:
determining, as a region flowing a leakage current no smaller than a predetermined value, one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said row selection lines;
determining, as a region flowing a leakage current no smaller than a predetermined value, one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said row selection lines,
said address output control signal to be supplied to said address signal output control circuit is a control signal for selecting said row selection lines by controlling the output of said row addressing signal in order to perform the determination of a defective cell.
In a preferred embodiment, further improvement resides in that, while the number of said row address decoders is 2n.
In a preferred embodiment, further improvement resides in that said semiconductor memory device is provided with n address buffers each of which is provided with two output terminals for taking control of the output signal of the 2n row address decoders, wherein n row addressing signals is input to the input terminal of said n address buffers,
wherein said address signal output control circuit serves to output signals to one terminals of the output terminals of said n address buffers in the same phase as said row addressing signals and to output signals to the other terminals of the output terminals of said n address buffers in the opposite phase to said row addressing signals in the case that said the operation mode switching signal indicate switching to the normal operation mode,
and serves to output signals to both the two output terminals of each of said n address buffers in the same phase as said row addressing signals in the case that said the operation mode switching signal indicate switching to the test operation mode.
In a preferred embodiment, further improvement resides in that said address output control signal is applied through existing I/O terminals which have provided for performing the read/write operation of user data.
In a preferred embodiment, further improvement resides in that said semiconductor memory device is provided with fuses provided between said common electric power source lines and the electric power source in order to separate a leakage current path when a defective cell is determined by the determination of a defective cell as recited.
In accordance with a further aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved semiconductor memory device comprising:
a memory cell array in which memory cells are arranged in the form of a matrix;
a plurality of word lines arranged within said memory cell array in the column direction of said memory cell, each of said word lines being connected to said memory cells respectively;
a plurality of bit lines arranged in the column direction of said memory cell array and connected to said memory cells;
a column selection circuit for selecting a desired bit line;
a test mode switching control circuit for disconnecting the respective bit lines from power source lines connected to one ends of said bit lines; and
a test mode electric power supply circuit for supplying an electric power source to the bit lines as selected on the test mode.
In a preferred embodiment, further improvement resides in that said semiconductor memory device is provided with fuses provided between said bit lines and the common electric power source line connected to ends of those bit lines.
In accordance with a further aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved semiconductor memory device comprising:
a memory cell array in which memory cells are arranged in the form of a matrix;
a plurality of word lines arranged within said memory cell array in the column direction of said memory cell, each of said word lines being connected to one ends of the data transfer gates of said memory cells respectively;
column address decoders for outputting a column selection signal to the column selection line on the basis of a column address signal;
a column selection switch for selecting a desired bit line among from the plurality of said bit lines on the basis of said column selection signal;
a plurality of data lines connected to the plurality of said bit lines through said column selection switch;
a test mode switching control circuit for disconnecting the respective bit lines from power source lines connected to one ends of said bit lines in the case that switching to a test mode is indicated by an operation mode switching signal which is used to switch between a normal operation mode and the test mode; and
a power terminal provided for leak test serving to supply an electric power source through said column selection switch to the bit lines as selected on the rest mode by means of said column selection switch for the purpose of detecting a leakage current through the bit lines.
In a preferred embodiment, further improvement resides in that said semiconductor memory device is provided with bit line equalizer circuits, bit line pull-up circuits and bit line load circuits connected respectively to one ends of said bit lines,
wherein said operation mode switching control circuit serves to disconnect the electric power supply to said bit lines by inactivating said bit line equalizer circuits, said bit line pull-up circuits and said bit line load circuits.
In a preferred embodiment, further improvement resides in that said semiconductor memory device is provided with data line equalizer circuits and data line pull-up circuits,
wherein said power terminal for leak test serving to supply an electric power source to said data line pull-up circuits and serving to supply the electric power source from said power terminal to the bit lines as selected on the test mode through said data line a pull-up circuits and said column selection switch for the purpose of detecting a leakage current through the bit lines.
In accordance with a further aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved semiconductor memory device comprising:
a memory cell array in which memory cells are arranged in the form of a matrix;
a plurality of word lines arranged within said memory cell array in the column direction of said memory cell, each of said word lines being connected to one ends of the data transfer gates of said memory cells respectively;
column address decoders for outputting a column selection signal to the column selection line on the basis of a column address signal;
a column selection switch for selecting a desired bit line among from the plurality of said bit lines on the basis of said column selection signal;
a plurality of data lines connected to the plurality of said bit lines through said column selection switch;
a test mode switching control circuit for cutting off the electric power supply through power source lines connected to one ends of said bit lines and through power source lines connected to a data lines in the case that switching to a test mode is indicated by an operation mode switching signal which is used to switch between a normal operation mode and the test mode;
a power terminal provided for leak rest through which an electric power source for test is supplied; and
a bit line leakage load circuit provided between the power source provided for test and a ground and serves to supply said electric power source only to the bit lines as selected by means of said column selection switch on the test mode for the purpose of detecting the leakage current through the bit lines.
In a preferred embodiment, further improvement resides in that said semiconductor memory device is provided with an address signal output control circuit serves to take control of the column address signal to be supplied to said column address decoders on the basis of an address output control signal as externally given in order to perform the determination of a defective bit line in the case that said the operation mode switching signal indicate switching to the test mode.
In a preferred embodiment, further improvement resides in that the determination of a defective cell is performed by:
determining, as a region flowing a leakage current no smaller than a predetermined value, one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines;
determining, as a region flowing a leakage current no smaller than a predetermined value, one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines,
said address signal output control circuit serves to take control of said column address signal for selecting said column selection line in order to perform the determination of a defective bit line.
In a preferred embodiment, further improvement resides in that, while the number of said column address decoders is 2n for outputting signals through 2n column selection lines,
said address signal output control circuit serves to select one of the 2n column selection lines in the case that said the operation mode switching signal indicate switching to the normal operation mode and to select 2n/2n lines, (m=1,2, . . . , n), of the 2n column selection lines in the case that said the operation mode switching signal indicate switching to the test operation mode.
In a preferred embodiment, further improvement resides in that said semiconductor memory device is provided with n address buffers each of which is provided with two output terminals for taking control of the output signal of the 2n column address decoders, wherein n column addressing signals is input to the input terminal of said n address buffers.
wherein said address signal output control circuit serves to output signals to one terminals of the output terminals of said n address buffers in the same phase as said column addressing signals and to output signals to the other terminals of the output terminals of said n address buffers in the opposite phase to said column addressing signals in the case that said the operation mode switching signal indicate switching to the normal operation mode, and serves to output signals to both the two output terminals of each of said n address buffers in the same phase as said column addressing signals in the case that said the operation mode switching signal indicate switching to the test operation mode.
In a preferred embodiment, further improvement resides in that said address output control signal is applied through existing I/O terminals which have provided for performing the read/write operation of user data.
In a preferred embodiment, further improvement resides in that said semiconductor memory device is provided with fuses provided between said bit lines and the common electric power source line connected to ends of those bit lines in order to break a leakage current path when a defective bit line is determined by the determination of a defective bit line as recited.